VIVADO – Learn From The Beginning! (With PCIe Full Project)
Learn how to use Vivado design suite to design Xilinx FPGA FROM ZERO using VHDL or VERILOG language!
What you’ll learn
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How to use Vivado
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Full Project with PCIe root complex to PCIe end point communication, how to setup the root complex and how to simulate the PCIe
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Adding IP to your project.
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Axi-Bus, Streamed and Memory-mapped IP’s and differences.
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Test Bench, what is it and how to write it
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How to simulate Vivado projects, using the Modelsim tool or Vivado.
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Zynq 7000, explained and implementation.
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Connecting Axi Bus to Zynq7000 peripherals and between IPs.
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Adding ILA ,integrated logic analyzer, the strongest tool for real-time debug.
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How to open SDK project
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More complex things you must know for using Vivado even in your working place as a professional!
Requirements
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Having a PC with windows/Linux and internet connection.
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Basic VHDL/Verilog Knowledge
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Installing Xilinx’s Vivado Design suite 2019, explained in the course.
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Installing ModelSim simulation tool, explained in the course.
Who this course is for:
- All Levels.
- Anyone who want to gain more knowledge and become a good FPGA developer from Zero.
- Anyone who wants to know how to work with Xilinx FPGAs.
- Anyone who wants to know how to work with VIVADO.
- Anyone who wants to know how to work with FPGA’s ZYNQ7000.
